Processor IP

Configurable Embedded RISC Processor IP

eSi-RISC is a highly configurable microprocessor architecture for embedded systems, that scales across a wide range of applications.

The eSi-RISC IP core has been silicon proven in a wide range of ASIC and FPGA technologies, from 0.35um to 16nm.

  • Configurable 16 or 32-bit, 5-stage pipelined RISC, load-store architecture.
  • Implemented in as little as 8k ASIC gates for minimum 16-bit configuration.
  • Intermixed 16 and 32-bit instructions gives exceptional code density.
  • Uses industry standard bus architecture for IP interconnection (AMBA AXI/AHB/APB).
  • Multiprocessor, SIMD and floating-point options.
  • Configurability and custom instructions will deliver a solution with exceptionally low-power.
  • Supports user and supervisor modes and HW nested interrupts.
  • JTAG or serial hardware debug, with optional trace.
  • Up to 4.12 CoreMark per MHz.

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eSi-RISC Product Family

eSi-1600

The eSi-1600 16-bit CPU core is a low-cost, low-power processor. It offers similar performance to more expensive 32-bit CPUs while having a system cost comparable to that of 8-bit CPUs.

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eSi-1650

The eSi-1650 16-bit CPU core is a small, low-power processor that includes an instruction cache. The cache provides a very power and area efficient solution for mature process nodes using OTP or Flash for program memory. It avoids the need for large on-chip shadow RAMs, whilst allowing the CPU to run at its maximum frequency, rather than be limited to the OTP/Flash frequency.

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eSi-3200

EnSilica’s cacheless eSi-3200 32-bit core is a small, low-power CPU particularly suited to embedded control applications. The CPU’s instruction set is configurable and can support 32×32->64 bit multiply and accumulate (MAC) as well as integer square root, CRC and other bit manipulation operations. It also has power management instructions.

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eSi-3250

EnSilica’s eSi-3250 32-bit CPU core is a high-performance processor ideal for integration into ASIC and/or FPGA designs with off-chip memories. It supports configurable instruction and data caches, from 1kB to 64kB. With the MMU option enabled, the eSi-3250 is suited to a wide range of applications including running complex operating systems such Linux.

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eSi-3260

EnSilica’s eSi-3260 32-bit CPU adds fixed-point SIMD (Single Instruction Multiple Data) DSP extensions, including a full complex multiply with rounding for FFT and FIRs. It is targeted specifically for applications needing DSP functionality with minimal silicon area and very low power including smart sensors, IoT sensing nodes and always-on applications such as voice command recognition.

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eSi-32X0fp

eSi-IP’s eSi-32X0fp 32-bit CPU is a member in the eSi-RISC family of processor cores.It is targeted specifically for applications needing to perform floating-point calculations with minimal silicon area and very low-power smart sensors, IoT sensing nodes and always-on applications such as voice command recognition.

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eSi-RISC IP Technical Overview

  • Benefits

    • Highly configurable, allowing the processor to be tailored to fit a wide range of applications, on both FPGA and ASIC technology.
    • Performance and code density amongst the very best available.
    • Silicon proven in multiple production devices.
    • License-free professional development suite using Eclipse and GNU tools.
    • Delivered as full integrated CPU sub-system to shorten time to market.
    • High quality support and documentation.
  • Development Kit

    A hardware development kit is available for evaluating these cores. This board provides a range of memory and external interfaces to suit most applications.

  • Toolchain

    RISC2
    The toolchain is based upon the industry standard GNU toolchain, which includes an optimising C and C++ compiler, assembler, linker, debugger, simulator and binary utilities. All these tools can be driven by the customisable Eclipse IDE (Integrated Development Environment). The toolchain is available for both Windows and Linux hosts and is available to use at no additional cost.

  • IP Delivery

    The eSi-RISC is implemented as a soft IP core, based on synthesisable Verilog RTL and can be easily ported to a wide range of ASIC processes and FPGAs. The design is DFT ready, supporting full scan insertion for all flip flops and memory BIST.

    A selection of AMBA peripherals are supplied with the core, including: UART, SPI, I2C™, Timer, PWM, Watchdog, GPIO, PS/2, Ethernet MAC as well as a static memory interface and DMA engine. By using an industry standard bus, a wide range of 3rd party IP cores can also be used.

  • Support

    By utilising eSi-IP’s system level design expertise to define the most appropriate configuration for your particular application and then using our design services to integrate the eSi-RISC core within your particular design, you can achieve a truly optimised solution without any of the pain often associated with embedded processor designs.

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