EnSilica present at DVCon Europe, 2015

DVCon2015_168_104The Design and Verification Conference (DVCon) Europe , held in Munich on 11/12th November 2015, is an important event for the European electronics industry – focusing on the practical use of EDA tools, standards, languages and methodologies for the design and verification of electronic systems and integrated circuits. This year, Paul Kaunds, Verification Consultant at EnSilica was selected to present at the conference.

One of the key themes of the conference was ‘Advanced Verification and Validation’ and Paul presented a 90min tutorial on the ‘Application of Design Patterns to Accelerate Development of Reusable, Configurable and portable UVCs’.

 The tutorial provided a background to the use of Design Patterns in areas such as software development, their influence on functional verification methodologies like UVM and how the same ideas can be used in building new UVCs which are inherently more reusable and portable – providing productivity and quality improvements for future projects.

 The slides from the presentation can be found here

 If you are interested in any of the ideas presented in the tutorial or would like to discuss any other verification challenges where EnSilica might be able to help, please contact us at www.ensilica.com/ip-testing-

 

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